1. Field of the Invention
The present invention relates generally to a method and apparatus for driving an alternating current plasma display panel (AC PDP), and, more particularly, to a method and apparatus for driving an alternating current plasma display panel, whereby image contrast is improved by reducing the emission of background light and an uniform and stable wall charge distribution is established over the entire panel though a relatively short reset time is used, thus allowing a subsequent data write operation to be easily performed.
2. Description of the Related Art
Various structures of Alternating Current (AC) Plasma Display Panels (PDPs) exist. Well-known and widely used ones of these structures are somewhat similar. A typical structure of AC PDPs is illustrated in FIG. 1. As illustrated in FIG. 1, an AC PDP includes an upper panel and a lower panel. The upper panel includes a glass substrate 51, a plurality of scan electrodes 69 and a plurality of sustain electrodes 79 arranged on the lower surface of the upper substrate to be parallel with one another, a dielectric layer 54 formed on the lower surface of the upper substrate on which the scan and sustain electrodes 69 and 79 have been formed, and a protective layer 55 formed on the dielectric layer 54. The lower substrate includes a back substrate 58, a plurality of addressing electrodes 89 arranged on the back substrate 58 to be perpendicular to the scanning and discharge sustain electrodes 69 and 79, a plurality of barrier walls 56 arranged to be parallel with the addressing electrodes 89 to partition cells from one another, and a phosphor layer 57. Discharge spaces between the upper panel and the lower panel are filled with a gas that can be ionized. A plurality of cells are formed around the discharge spaces where the scan electrodes 69, the discharge sustain electrodes 79 being parallel to the scan electrode 79 and the addressing electrodes 89 running in a direction intersecting the scan electrodes and the discharge sustain electrodes. Every three types of cells exhibiting red, green and blue colors, respectively, form a single pixel to provide various colors.
Voltages actually applied to the discharge spaces may be different from voltages applied to the electrodes due to wall voltages resulting from wall charges. Fundamental voltages concerned with the operations of the PDP to be described below are defined as follows. The value obtained by adding an externally applied voltage between the scan and the sustain electrodes and a wall voltage between the scan and the sustain electrodes due to the accumulated wall charge is defined as a voltage across the discharge space 75, while the value obtained by adding an externally applied voltage between the scan and the address electrodes and a wall voltage between the scan and the address electrodes due to the accumulated wall charge is defined as a voltage difference between scan and address electrodes.
A conventional basic method of driving the panels 50 is described below. A write discharge is generated by selectively applying an address voltage exceeding the firing voltage to a discharge space defined by the row electrodes 69 and 79 and column electrode 89 of a cell selected in accordance with image data. Thereafter, an image is represented by generating sustain discharges in such a way as to alternately apply sustain voltages to the scan electrodes 69 and the sustain electrodes 79 to such an extent that the sustain discharges are generated in cells where the write discharges have been generated by the application of the address voltages but the sustain discharges are not generated in cells where the write discharges have not been generated. This technique utilizes “a memory effect” resulting from a wall voltage, which is the unique characteristic of an AC PDP. The voltage to be applied to the discharge space is blocked by the wall voltages generated by the accumulation of electrons and ions on the dielectric layer 54 and the protective layer 55. These accumulated electrons and ions remain till a next discharge, and a voltage (that is, a wall voltage) resulting from these accumulated electrons and ions is added to a currently applied pulse voltage, so a high voltage is applied to the discharge space to facilitate a discharge. This action of the wall charge is called the memory effect.
Accordingly, in order to reliably drive the AC PDP, it is important to control the amounts of the accumulated wall charges to be constant during reset operation. Additionally, data write (address) and discharge sustain operations are stably accomplished by controlling a certain amount of wall charge desired by a designer to be accumulated during the reset period, regardless of the generation of discharge at the corresponding cell during the previous sustain period (that is, without the influence of the memory effect resulting from wall charges accumulated during the previous sustain period).
For a conventional reset method for reliably driving an AC PDP, there is a method of controlling wall charge status over an entire screen by carrying out an erase discharge, a write discharge and another erase discharge over an entire screen, which was first introduced in Yoshikawa el al., “A Full Color AC Plasma Display with 256 Gray Scale,” Japan Display, 1992, pp 605˜608. Thereafter, it was disclosed that a reset operation using a ramp-shaped waveform can achieve the stabilization of operation as well as the improvement of image contrast, in the thesis of Larry F. Weber, “Plasma Display Device Challenges,” Asia Display, 1998, pp 15–27, and the technique of the thesis was issued as U.S. Pat. No. 5,745,086 entitled “Plasma Panel Exhibiting Enhanced Contrast.”
In the driving method proposed by Yoshikawa et al. 8 sub-fields having different brightness are provided in one Television (TV) frame (generally, 16.7 ms) to represent 256 gray scale levels and each of the 8 sub-fields is divided into an address period and a sustain period. That is, the 8 sub-fields have the relative lengths of sustain periods corresponding to 20, 21, 22, 23, 24, 25, 26 and 27, and 256 (=28) gray scale levels can be represented by the combination of the sub-fields. In the sustain period, discharges are generated in only discharge spaces turned on during the address period by alternately applying sustain pulses to the scan and sustain electrodes 69 and 79, so that luminances are implemented to be proportional to the number of the sustain pulses. A voltage of a magnitude, which is sufficient to generate a sustain discharge in a discharge space turned ON during the address period and is insufficient to generate a sustain discharge in a discharge space turned OFF during the address period, is used as a sustain voltage Vs.
FIG. 3 shows an example of driving waveforms employed during a single sub-field shown in FIG. 2. In order to write data while sequentially selecting rows at step 4 of an address period in a sub-field regardless of whether the sustain discharge were turned on or not in a previous field, preparatory steps, that is, steps 1 to 3 (having an identical function with a reset period of another prior art shown in FIG. 4), are required. At the beginning stage of the step 2 which follows the step 1, a strong discharge is formed due to a high voltage pulse (write pulse) applied between the scan electrode 69 (Y electrode) and the sustain electrode 79 (X electrode), so that a wall voltage of a similar magnitude with the write pulse is formed between the electrodes 69 and 79, as a result of wall charge accumulation in the discharge cell. At the end of the step 2, because the externally applied pulse voltage falls to a reference voltage, only the wall voltage is remained in the discharge space. Therefore, a self-erasing discharge due to the wall voltage is formed and the wall voltage disappears by the wall charge erasing effect of the self-erasing discharge. Accordingly, the address period is initiated in condition that the wall voltages in all of the discharge cells are annihilated to 0 V. After that, in the step 4, address discharges are formed in each of the rows over the panel by applying data pulses VA to the address electrodes 89, the data pulses synchronized with scan pulses which are applied to the scan electrodes.
An object that Yoshikawa et al. attempted to achieve through the provision of the steps 1 to 3 is to overcome problems that can be caused by the various distributions of wall charges over the discharge spaces distributed on the panel. In Larry F. Weber's patent, the period of the steps is called a set-up period (corresponding to a reset period 10 in an embodiment of the present invention) General requirements of the set-up period are as follows:
First, the set-up period must function to prime discharge spaces so as to perform reliable driving in selective address and sustain periods thereafter.
Second, the set-up period must uniformly establish a predetermined amount of wall voltage required for a stable operation in a given sub-field. The amount of wall voltage is determined according to a degree required to allow a selective write operation to be normally performed during the address period of each sub-field. A very important point is that a predetermined amount of wall voltage, which must be established during the set-up period of a given sub-field, must not be affected by the amount of wall voltage that remains from the previous sub-field. If predetermined amounts of wall voltages of some discharge cells are affected by the status of the previous sub-field, the distributions of wall voltages over discharge cells become uneven. As a result, the selective write operation or the sustain operation may be erroneously performed.
In conclusion, the driving for the reset period must be designed to assure stability. Additionally, to what extent the following requirements are achieved can be another criterion to evaluate performances of various driving methods used for the reset period.
First, a darkroom contrast ratio should be considered. There are two methods for improving the darkroom contrast ratio, that is, a method of increasing maximum brightness by improving discharge efficiency and luminance, increasing the number of sustain pulses, etc. and a method of reducing emission which is not related to the luminance level corresponding to the image data, that is, “background luminance”. If the emission during a reset period, which has no relation with the level of the image data, is reduced, “background luminance” is decreased, so that the darkroom contrast ratio can be improved.
Second, the magnitude of usable voltage applied to the address electrode at the time of writing data after the reset period, that is, “an address margin,” must be assured. The discharge characteristics of discharge spaces distributed over the screen of an AC PDP may deviate somewhat, and are significantly affected by circumstances around the discharge spaces. When “stability” is not only provided by establishing uniformity through the reset period so as to prevent the address discharges from being affected by such various circumstances, but addressing is also performed at a minimized address voltage, it can be stated that the address margin is sufficiently assured.
Third, the “time” required for the reset period must be reduced. In the driving method exemplified in FIG. 2 as a prior art, progressive scanning is performed 8 times for 480 (or more) lines to represent a single frame. For one basic method for correcting the error of the image representation of a PDP known as “dynamic false contour”, there is used a method in which a single frame is composed of not 8 sub-fields but 10 to 12 sub-fields by increasing the number of sub-fields. Accordingly, if the time required for a single reset period is 300 us, the case where scanning is carried out 8 times requires 2.4 ms, and the case where scanning is carried out 12 times requires 3.6 ms. In these cases, the reset time occupies a considerable part of the 1/60 s, that is, 16.7 ms, given for a single frame. If the reset time is reduced to approximately 100 us, the reset time in a single frame becomes just 1.2 ms for the case where scanning is carried out 12 times. This fact allows a sub-field to be added or the sustain period to be lengthened for the period of 2.4 ms by which the reset period is reduced compared to the former lengthy reset period. The larger the number of sub-fields obtained by dividing a single frame, the more important the necessity for the reduction of the reset period become.
Of conventional voltage waveforms for the reset period, voltage waveforms used in the reset method proposed by Yoshikawa et al. are shown in FIG. 3. The waveforms of this method are referred to as “strong pulse reset waveforms.” This method assures “stability” over all the discharge spaces of an entire screen by generating strong write discharges and self-erasing discharges between erase discharge pulses over the entire panel. In this method, the strong write discharge of step 2 is generated by the voltage higher than a sustain voltage, so that very strong light is emitted. Accordingly, since in this method, the background luminance level is considerably high, and this method is disadvantageous in that darkroom contrast ratio is low. It is known that this method assures a desirable address margin. It is also known that waveforms with lengthy time constants and low voltage are applied as the two erase pulses, which causes the time required for the reset period to be relatively long.
Of the conventional reset methods using various voltage waveforms, there is a reset method using a ramp waveform. In this reset method, wall voltage is controlled by the waveforms shown in FIG. 4. In this case, a ramp waveform having a constant slope is used to maintain a weak discharge mode that desirably controls the wall voltage. When the ramp waveform is limited to a considerably small slope (<10V/us), stability and address margin requirements are sufficiently fulfilled and the background luminance can be suppressed to a considerably low level compared to other conventional reset methods. However, in this case, the time required for the reset period must be lengthened.
As described above, stability is the basic requirement for the reset period, and it is important to achieve three other requirements, that is, a sufficiently low background luminance level, the assurance of an address margin and a short reset period, while achieving the stability of these three requirements, the assurance of the address margin is a requirement that must be fulfilled to a certain extent, and the reductions in background luminance and the reset period are requirements that are necessary to obtain improved image quality.
Further, the background luminance is concerned with the absolute intensity of a discharge occurring during the reset period. The background luminance is very important in that, as the background luminance decreases, the image contrast increases and clearer image quality can be obtained.
The reduction in the time required for a reset operation contributes to an improvement in the performance of a PDP in various aspects. The remaining time can be assigned to the sustain period by reducing the time required for the reset period, which results in the increase of brightness. Meanwhile, when the number of sub-fields is desired to be increased to 8 or more to overcome the dynamic false contour problem that impedes the implementation of motion images of a PDP, a much faster reset operation is required. Further, since much time must be assigned to the address period when the number of scan electrodes is increased according to an increase in the resolution of images to implement, a still faster reset operation is also required in this case.